Different Factors that affect the performance of pipelined system

Hello readers!

Today we are going to discuss about DIFFERENT FACTORS THAT AFFECT THE PERFORMANCE OF THE PIPELINE

Here we go!
Basically you need to know what is pipelining before we come the above said topic 
PIPELINING: The fetch cycle, decode cycle and the execute cycle for several instructions are performed simultaneously to reduce overall processing time. This process is referred to as pipelining.

PERFORMANCE
  • The pipelining process shown in timing diagram is straight forward, the performance enhancement is limited by several factors. They are:

  1. Timing diagram shown in fig 3.(effect of conditional branch) assumes that each instruction goes through all five stages of the pipeline. This will not always be the case. For ex, a load instruction does not need SR stage. Therefore, there will be some waiting involved at various pipeline stages.
  2. Timing diagram assumes that all of the stages can be performed simultaneously. In particular FI(fetch instruction), FO(fetch operand) and SR(store result) require memory access. Due to memory conflicts, most memory systems do not permit simultaneous memory access.
  3. The conditional branch instruction invalidates several instruction fetches. This is shown in fig below

Fig
That's all!
I hope you understood it better.
Thank you
                                                                *****


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